IEICE TRANSACTIONS on Fundamentals
Effects of On-Chip Inductance on Power Distribution Grid
Summary :
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3564-3572
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3564
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Keyword
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Atsushi MURAMATSU, Masanori HASHIMOTO, Hidetoshi ONODERA, "Effects of On-Chip Inductance on Power Distribution Grid" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3564-3572, December 2005, doi: 10.1093/ietfec/e88-a.12.3564.
Abstract: With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3564/_p
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@ARTICLE{e88-a_12_3564,
author={Atsushi MURAMATSU, Masanori HASHIMOTO, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Effects of On-Chip Inductance on Power Distribution Grid},
year={2005},
volume={E88-A},
number={12},
pages={3564-3572},
abstract={With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3564},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Effects of On-Chip Inductance on Power Distribution Grid
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3564
EP - 3572
AU - Atsushi MURAMATSU
AU - Masanori HASHIMOTO
AU - Hidetoshi ONODERA
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3564
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.
ER -
English
