Unified Phase Compiler by Use of 3-D Representation Space
Summary :
A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.838-845
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.4.838
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takefumi MIYOSHI, Nobuhiko SUGINO, "Unified Phase Compiler by Use of 3-D Representation Space" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 4, pp. 838-845, April 2005, doi: 10.1093/ietfec/e88-a.4.838.
Abstract: A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.838/_p
Copy
@ARTICLE{e88-a_4_838,
author={Takefumi MIYOSHI, Nobuhiko SUGINO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Unified Phase Compiler by Use of 3-D Representation Space},
year={2005},
volume={E88-A},
number={4},
pages={838-845},
abstract={A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.},
keywords={},
doi={10.1093/ietfec/e88-a.4.838},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Unified Phase Compiler by Use of 3-D Representation Space
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 838
EP - 845
AU - Takefumi MIYOSHI
AU - Nobuhiko SUGINO
PY - 2005
DO - 10.1093/ietfec/e88-a.4.838
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.
ER -
English
