IEICE TRANSACTIONS on Fundamentals
A New Application-Specific PLD Architecture
Summary :
A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.6 pp.1425-1433
- Publication Date
- 2005/06/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.6.1425
- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004))
- Category
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Jae-Jin LEE, Gi-Yong SONG, "A New Application-Specific PLD Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 6, pp. 1425-1433, June 2005, doi: 10.1093/ietfec/e88-a.6.1425.
Abstract: A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.6.1425/_p
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@ARTICLE{e88-a_6_1425,
author={Jae-Jin LEE, Gi-Yong SONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Application-Specific PLD Architecture},
year={2005},
volume={E88-A},
number={6},
pages={1425-1433},
abstract={A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.},
keywords={},
doi={10.1093/ietfec/e88-a.6.1425},
ISSN={},
month={June},}
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TY - JOUR
TI - A New Application-Specific PLD Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1425
EP - 1433
AU - Jae-Jin LEE
AU - Gi-Yong SONG
PY - 2005
DO - 10.1093/ietfec/e88-a.6.1425
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2005
AB - A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.
ER -
English
