IEICE TRANSACTIONS on Fundamentals
Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
Summary :
High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3427-3434
- Publication Date
- 2006/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.12.3427
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- System Level Design
Authors
Keyword
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Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, Shinji KIMURA, "Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3427-3434, December 2006, doi: 10.1093/ietfec/e89-a.12.3427.
Abstract: High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3427/_p
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@ARTICLE{e89-a_12_3427,
author={Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique},
year={2006},
volume={E89-A},
number={12},
pages={3427-3434},
abstract={High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3427},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3427
EP - 3434
AU - Nobuhiro DOI
AU - Takashi HORIYAMA
AU - Masaki NAKANISHI
AU - Shinji KIMURA
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3427
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.
ER -
English
