A 0.3-V Operating, <I>V</I><SUB>th</SUB>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Yasuhiro MORITA; Hidehiro FUJIWARA; Hiroki NOGUCHI; Kentaro KAWAKAMI; Junichi MIYAKOSHI; Shinji MIKAMI; Koji NII; Hiroshi KAWAGUCHI; Masahiko YOSHIMOTO

doi:10.1093/ietfec/e89-a.12.3634

A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

Full Text Views

0

Cite this

Summary :

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3634-3641

Publication Date: 2006/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.12.3634

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: VLSI Architecture

Cite this

Copy

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 12, pp. 3634-3641, December 2006, doi: 10.1093/ietfec/e89-a.12.3634.
Abstract: We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3634/_p

Copy

@ARTICLE{e89-a_12_3634,
author={Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond},
year={2006},
volume={E89-A},
number={12},
pages={3634-3641},
abstract={We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3634},
ISSN={1745-1337},
month={December},}

Copy

TY - JOUR
TI - A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3634
EP - 3641
AU - Yasuhiro MORITA
AU - Hidehiro FUJIWARA
AU - Hiroki NOGUCHI
AU - Kentaro KAWAKAMI
AU - Junichi MIYAKOSHI
AU - Shinji MIKAMI
AU - Koji NII
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3634
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.
ER -