IEICE TRANSACTIONS on Fundamentals
Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis
Summary :
We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.4 pp.875-878
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.4.875
- Type of Manuscript
- LETTER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
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Eui-Young CHUNG, Hyuk-Jun LEE, Sung Woo CHUNG, "Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 4, pp. 875-878, April 2007, doi: 10.1093/ietfec/e90-a.4.875.
Abstract: We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.4.875/_p
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@ARTICLE{e90-a_4_875,
author={Eui-Young CHUNG, Hyuk-Jun LEE, Sung Woo CHUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis},
year={2007},
volume={E90-A},
number={4},
pages={875-878},
abstract={We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.},
keywords={},
doi={10.1093/ietfec/e90-a.4.875},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 875
EP - 878
AU - Eui-Young CHUNG
AU - Hyuk-Jun LEE
AU - Sung Woo CHUNG
PY - 2007
DO - 10.1093/ietfec/e90-a.4.875
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2007
AB - We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.
ER -
English
