IEICE TRANSACTIONS on Fundamentals
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
Summary :
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3481-3487
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3481
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Keyword
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Shinya ABE, Masanori HASHIMOTO, Takao ONOYE, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3481-3487, December 2008, doi: 10.1093/ietfec/e91-a.12.3481.
Abstract: Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3481/_p
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@ARTICLE{e91-a_12_3481,
author={Shinya ABE, Masanori HASHIMOTO, Takao ONOYE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution},
year={2008},
volume={E91-A},
number={12},
pages={3481-3487},
abstract={Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3481},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3481
EP - 3487
AU - Shinya ABE
AU - Masanori HASHIMOTO
AU - Takao ONOYE
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3481
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
ER -
English
