IEICE TRANSACTIONS on Fundamentals
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
Summary :
This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60 hrs. to 3 hrs. in case of 42M-gate LSIs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3524-3530
- Publication Date
- 2008/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.12.3524
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Keyword
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Keiichi SUEMITSU, Toshiaki ITO, Toshiki KANAMOTO, Masayuki TERAI, Satoshi KOTANI, Shigeo SAWADA, "A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3524-3530, December 2008, doi: 10.1093/ietfec/e91-a.12.3524.
Abstract: This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60 hrs. to 3 hrs. in case of 42M-gate LSIs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3524/_p
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@ARTICLE{e91-a_12_3524,
author={Keiichi SUEMITSU, Toshiaki ITO, Toshiki KANAMOTO, Masayuki TERAI, Satoshi KOTANI, Shigeo SAWADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults},
year={2008},
volume={E91-A},
number={12},
pages={3524-3530},
abstract={This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60 hrs. to 3 hrs. in case of 42M-gate LSIs.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3524},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3524
EP - 3530
AU - Keiichi SUEMITSU
AU - Toshiaki ITO
AU - Toshiki KANAMOTO
AU - Masayuki TERAI
AU - Satoshi KOTANI
AU - Shigeo SAWADA
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3524
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60 hrs. to 3 hrs. in case of 42M-gate LSIs.
ER -
English
