Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Kazunori SHIMIZU; Nozomu TOGAWA; Takeshi IKENAGA; Satoshi GOTO

doi:10.1093/ietfec/e91-a.4.1054

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Kazunori SHIMIZU, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO

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Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.4 pp.1054-1061

Publication Date: 2008/04/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.4.1054

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)

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Kazunori SHIMIZU, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO, "Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 4, pp. 1054-1061, April 2008, doi: 10.1093/ietfec/e91-a.4.1054.
Abstract: Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.4.1054/_p

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@ARTICLE{e91-a_4_1054,
author={Kazunori SHIMIZU, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique},
year={2008},
volume={E91-A},
number={4},
pages={1054-1061},
abstract={Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.},
keywords={},
doi={10.1093/ietfec/e91-a.4.1054},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1054
EP - 1061
AU - Kazunori SHIMIZU
AU - Nozomu TOGAWA
AU - Takeshi IKENAGA
AU - Satoshi GOTO
PY - 2008
DO - 10.1093/ietfec/e91-a.4.1054
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2008
AB - Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.
ER -