IEICE TRANSACTIONS on Fundamentals
Prciseness of Discrete Time Verification
Summary :
The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the deisrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then u is the expected unit time.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.10 pp.1755-1759
- Publication Date
- 1993/10/25
- Publicized
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Shinji KIMURA, Shunsuke TSUBOTA, Hiromasa HANEDA, "Prciseness of Discrete Time Verification" in IEICE TRANSACTIONS on Fundamentals,
vol. E76-A, no. 10, pp. 1755-1759, October 1993, doi: .
Abstract: The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the deisrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then u is the expected unit time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_10_1755/_p
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@ARTICLE{e76-a_10_1755,
author={Shinji KIMURA, Shunsuke TSUBOTA, Hiromasa HANEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Prciseness of Discrete Time Verification},
year={1993},
volume={E76-A},
number={10},
pages={1755-1759},
abstract={The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the deisrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then u is the expected unit time.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Prciseness of Discrete Time Verification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1755
EP - 1759
AU - Shinji KIMURA
AU - Shunsuke TSUBOTA
AU - Hiromasa HANEDA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1993
AB - The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the deisrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then u is the expected unit time.
ER -
English
