IEICE TRANSACTIONS on Fundamentals
Modularization and Processor Placement for DSP Neo-Systolic Array
Summary :
A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.
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- IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.3 pp.349-361
- Publication Date
- 1993/03/25
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- Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
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Kazuhito ITO, Kesami HAGIWARA, Takashi SHIMIZU, Hiroaki KUNIEDA, "Modularization and Processor Placement for DSP Neo-Systolic Array" in IEICE TRANSACTIONS on Fundamentals,
vol. E76-A, no. 3, pp. 349-361, March 1993, doi: .
Abstract: A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_3_349/_p
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@ARTICLE{e76-a_3_349,
author={Kazuhito ITO, Kesami HAGIWARA, Takashi SHIMIZU, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modularization and Processor Placement for DSP Neo-Systolic Array},
year={1993},
volume={E76-A},
number={3},
pages={349-361},
abstract={A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Modularization and Processor Placement for DSP Neo-Systolic Array
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 349
EP - 361
AU - Kazuhito ITO
AU - Kesami HAGIWARA
AU - Takashi SHIMIZU
AU - Hiroaki KUNIEDA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1993
AB - A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.
ER -
English
