IEICE TRANSACTIONS on Fundamentals
Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Summary :
The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.6 pp.904-910
- Publication Date
- 1993/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
- Category
- Parallel Processor Scheduling
Authors
Keyword
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Bumchul KIM, Michitaka KAMEYAMA, Tatsuo HIGUCHI, "Unified Scheduling of High Performance Parallel VLSI Processors for Robotics" in IEICE TRANSACTIONS on Fundamentals,
vol. E76-A, no. 6, pp. 904-910, June 1993, doi: .
Abstract: The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_6_904/_p
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@ARTICLE{e76-a_6_904,
author={Bumchul KIM, Michitaka KAMEYAMA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Unified Scheduling of High Performance Parallel VLSI Processors for Robotics},
year={1993},
volume={E76-A},
number={6},
pages={904-910},
abstract={The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 904
EP - 910
AU - Bumchul KIM
AU - Michitaka KAMEYAMA
AU - Tatsuo HIGUCHI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1993
AB - The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.
ER -
English
