A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers

Satomi OGAWA; Kenzo WATANABE

A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers

Satomi OGAWA, Kenzo WATANABE

Full Text Views

0

Cite this

Summary :

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.6 pp.924-930

Publication Date: 1993/06/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))

Category: Methods and Circuits for Signal Processing

Cite this

Copy

Satomi OGAWA, Kenzo WATANABE, "A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers" in IEICE TRANSACTIONS on Fundamentals, vol. E76-A, no. 6, pp. 924-930, June 1993, doi: .
Abstract: A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_6_924/_p

Copy

@ARTICLE{e76-a_6_924,
author={Satomi OGAWA, Kenzo WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers},
year={1993},
volume={E76-A},
number={6},
pages={924-930},
abstract={A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.},
keywords={},
doi={},
ISSN={},
month={June},}

Copy

TY - JOUR
TI - A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 924
EP - 930
AU - Satomi OGAWA
AU - Kenzo WATANABE
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1993
AB - A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.
ER -