Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator

Yasukazu IWASAKI; Kunihiro ASADA

Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator

Yasukazu IWASAKI, Kunihiro ASADA

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A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.2 pp.371-379

Publication Date: 1994/02/25

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Type of Manuscript: Special Section PAPER (Special Section on High-Performance MOS Analog Circuits)

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Yasukazu IWASAKI, Kunihiro ASADA, "Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator" in IEICE TRANSACTIONS on Fundamentals, vol. E77-A, no. 2, pp. 371-379, February 1994, doi: .
Abstract: A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_2_371/_p

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@ARTICLE{e77-a_2_371,
author={Yasukazu IWASAKI, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator},
year={1994},
volume={E77-A},
number={2},
pages={371-379},
abstract={A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 371
EP - 379
AU - Yasukazu IWASAKI
AU - Kunihiro ASADA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1994
AB - A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.
ER -