IEICE TRANSACTIONS on Fundamentals
High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters
Summary :
This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.6 pp.944-949
- Publication Date
- 1994/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
- Category
- Digital Signal Processing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yoshitaka TSUNEKAWA, Kyousiro SEKI, "High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters" in IEICE TRANSACTIONS on Fundamentals,
vol. E77-A, no. 6, pp. 944-949, June 1994, doi: .
Abstract: This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_6_944/_p
Copy
@ARTICLE{e77-a_6_944,
author={Yoshitaka TSUNEKAWA, Kyousiro SEKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters},
year={1994},
volume={E77-A},
number={6},
pages={944-949},
abstract={This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 944
EP - 949
AU - Yoshitaka TSUNEKAWA
AU - Kyousiro SEKI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1994
AB - This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.
ER -
English
