IEICE TRANSACTIONS on Fundamentals
An Instruction Set Optimization Algorithm for Pipelined ASIPs
Summary :
This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1707-1714
- Publication Date
- 1995/12/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, Nobuyuki HIKICHI, "An Instruction Set Optimization Algorithm for Pipelined ASIPs" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 12, pp. 1707-1714, December 1995, doi: .
Abstract: This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_12_1707/_p
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@ARTICLE{e78-a_12_1707,
author={Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, Nobuyuki HIKICHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Instruction Set Optimization Algorithm for Pipelined ASIPs},
year={1995},
volume={E78-A},
number={12},
pages={1707-1714},
abstract={This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - An Instruction Set Optimization Algorithm for Pipelined ASIPs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1707
EP - 1714
AU - Nguyen Ngoc BINH
AU - Masaharu IMAI
AU - Akichika SHIOMI
AU - Nobuyuki HIKICHI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1995
AB - This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.
ER -
English
