VLSI Cell Placement on Arbitrarily-Shaped Rectilinear Regions Using Neural Networks with Calibration Nodes

Ray-I CHANG; Pei-Yung HSIAO

VLSI Cell Placement on Arbitrarily-Shaped Rectilinear Regions Using Neural Networks with Calibration Nodes

Ray-I CHANG, Pei-Yung HSIAO

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In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1777-1784

Publication Date: 1995/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Ray-I CHANG, Pei-Yung HSIAO, "VLSI Cell Placement on Arbitrarily-Shaped Rectilinear Regions Using Neural Networks with Calibration Nodes" in IEICE TRANSACTIONS on Fundamentals, vol. E78-A, no. 12, pp. 1777-1784, December 1995, doi: .
Abstract: In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_12_1777/_p

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@ARTICLE{e78-a_12_1777,
author={Ray-I CHANG, Pei-Yung HSIAO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Cell Placement on Arbitrarily-Shaped Rectilinear Regions Using Neural Networks with Calibration Nodes},
year={1995},
volume={E78-A},
number={12},
pages={1777-1784},
abstract={In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - VLSI Cell Placement on Arbitrarily-Shaped Rectilinear Regions Using Neural Networks with Calibration Nodes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1777
EP - 1784
AU - Ray-I CHANG
AU - Pei-Yung HSIAO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1995
AB - In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.
ER -