Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.

In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.