Power and Area Minimization by Reorganizing CMOS Complex-Gates

Masayoshi TACHIBANA; Sachiko KUROSAWA; Reiko NOJIMA; Naohito KOJIMA; Masaaki YAMADA; Takashi MITSUHASHI; Nobuyuki GOTO

Power and Area Minimization by Reorganizing CMOS Complex-Gates

Masayoshi TACHIBANA, Sachiko KUROSAWA, Reiko NOJIMA, Naohito KOJIMA, Masaaki YAMADA, Takashi MITSUHASHI, Nobuyuki GOTO

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This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.3 pp.312-320

Publication Date: 1996/03/25

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Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)

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Masayoshi TACHIBANA, Sachiko KUROSAWA, Reiko NOJIMA, Naohito KOJIMA, Masaaki YAMADA, Takashi MITSUHASHI, Nobuyuki GOTO, "Power and Area Minimization by Reorganizing CMOS Complex-Gates" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 3, pp. 312-320, March 1996, doi: .
Abstract: This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_3_312/_p

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@ARTICLE{e79-a_3_312,
author={Masayoshi TACHIBANA, Sachiko KUROSAWA, Reiko NOJIMA, Naohito KOJIMA, Masaaki YAMADA, Takashi MITSUHASHI, Nobuyuki GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power and Area Minimization by Reorganizing CMOS Complex-Gates},
year={1996},
volume={E79-A},
number={3},
pages={312-320},
abstract={This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Power and Area Minimization by Reorganizing CMOS Complex-Gates
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 312
EP - 320
AU - Masayoshi TACHIBANA
AU - Sachiko KUROSAWA
AU - Reiko NOJIMA
AU - Naohito KOJIMA
AU - Masaaki YAMADA
AU - Takashi MITSUHASHI
AU - Nobuyuki GOTO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1996
AB - This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.
ER -