IEICE TRANSACTIONS on Fundamentals
Optimal Instruction Set Design through Adaptive Detabase Generation
Summary :
This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.3 pp.347-353
- Publication Date
- 1996/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
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Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, Nobuyuki HIKICHI, "Optimal Instruction Set Design through Adaptive Detabase Generation" in IEICE TRANSACTIONS on Fundamentals,
vol. E79-A, no. 3, pp. 347-353, March 1996, doi: .
Abstract: This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_3_347/_p
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@ARTICLE{e79-a_3_347,
author={Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, Nobuyuki HIKICHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimal Instruction Set Design through Adaptive Detabase Generation},
year={1996},
volume={E79-A},
number={3},
pages={347-353},
abstract={This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Optimal Instruction Set Design through Adaptive Detabase Generation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 347
EP - 353
AU - Nguyen Ngoc BINH
AU - Masaharu IMAI
AU - Akichika SHIOMI
AU - Nobuyuki HIKICHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1996
AB - This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.
ER -
English
