A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code

Kazumasa KOBAYASHI; Kouji YAMANO; Hideki KOKUBUN; Kiichi KOBAYASHI

A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code

Kazumasa KOBAYASHI, Kouji YAMANO, Hideki KOKUBUN, Kiichi KOBAYASHI

Full Text Views

0

Cite this

Summary :

A new high-speed decoding algorithm for Difference-set cyclic codes, and the design and implementation of a 50 MHz CMOS LSI for decoding the (1057, 813) DSCC, are presented. The algorithm, called modified threshold decoding, makes it possible to introduce an arbitrary number of pipeline stages into feedback loops in decoding circuits. A prototype LSI containing about 13k logic gates was fabricated using 1 µm CMOS gate-array technology. The power consumption is less than 750 mW at a 50 MHz clock rate. It is available for digital data transmission systems having an I/O data rate of up to 25 MBPS. It is being used in experimental set-ups targeted at future digital broadcasting systems. The proposed algorithm has an important advantage for much longer codes as it has the potential to be used in the high-speed decoding of DSCCs having a code length longer than 1057.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.7 pp.1060-1067

Publication Date: 1996/07/25

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

Cite this

Copy

Kazumasa KOBAYASHI, Kouji YAMANO, Hideki KOKUBUN, Kiichi KOBAYASHI, "A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 7, pp. 1060-1067, July 1996, doi: .
Abstract: A new high-speed decoding algorithm for Difference-set cyclic codes, and the design and implementation of a 50 MHz CMOS LSI for decoding the (1057, 813) DSCC, are presented. The algorithm, called modified threshold decoding, makes it possible to introduce an arbitrary number of pipeline stages into feedback loops in decoding circuits. A prototype LSI containing about 13k logic gates was fabricated using 1 µm CMOS gate-array technology. The power consumption is less than 750 mW at a 50 MHz clock rate. It is available for digital data transmission systems having an I/O data rate of up to 25 MBPS. It is being used in experimental set-ups targeted at future digital broadcasting systems. The proposed algorithm has an important advantage for much longer codes as it has the potential to be used in the high-speed decoding of DSCCs having a code length longer than 1057.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_7_1060/_p

Copy

@ARTICLE{e79-a_7_1060,
author={Kazumasa KOBAYASHI, Kouji YAMANO, Hideki KOKUBUN, Kiichi KOBAYASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code},
year={1996},
volume={E79-A},
number={7},
pages={1060-1067},
abstract={A new high-speed decoding algorithm for Difference-set cyclic codes, and the design and implementation of a 50 MHz CMOS LSI for decoding the (1057, 813) DSCC, are presented. The algorithm, called modified threshold decoding, makes it possible to introduce an arbitrary number of pipeline stages into feedback loops in decoding circuits. A prototype LSI containing about 13k logic gates was fabricated using 1 µm CMOS gate-array technology. The power consumption is less than 750 mW at a 50 MHz clock rate. It is available for digital data transmission systems having an I/O data rate of up to 25 MBPS. It is being used in experimental set-ups targeted at future digital broadcasting systems. The proposed algorithm has an important advantage for much longer codes as it has the potential to be used in the high-speed decoding of DSCCs having a code length longer than 1057.},
keywords={},
doi={},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1060
EP - 1067
AU - Kazumasa KOBAYASHI
AU - Kouji YAMANO
AU - Hideki KOKUBUN
AU - Kiichi KOBAYASHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 1996
AB - A new high-speed decoding algorithm for Difference-set cyclic codes, and the design and implementation of a 50 MHz CMOS LSI for decoding the (1057, 813) DSCC, are presented. The algorithm, called modified threshold decoding, makes it possible to introduce an arbitrary number of pipeline stages into feedback loops in decoding circuits. A prototype LSI containing about 13k logic gates was fabricated using 1 µm CMOS gate-array technology. The power consumption is less than 750 mW at a 50 MHz clock rate. It is available for digital data transmission systems having an I/O data rate of up to 25 MBPS. It is being used in experimental set-ups targeted at future digital broadcasting systems. The proposed algorithm has an important advantage for much longer codes as it has the potential to be used in the high-speed decoding of DSCCs having a code length longer than 1057.
ER -