IEICE TRANSACTIONS on Fundamentals
A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs
Summary :
This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1842-1852
- Publication Date
- 1997/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Tsunemasa HAYASHI, Atsushi TAKAHARA, Kennosuke FUKAMI, "A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1842-1852, October 1997, doi: .
Abstract: This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1842/_p
Copy
@ARTICLE{e80-a_10_1842,
author={Tsunemasa HAYASHI, Atsushi TAKAHARA, Kennosuke FUKAMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs},
year={1997},
volume={E80-A},
number={10},
pages={1842-1852},
abstract={This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1842
EP - 1852
AU - Tsunemasa HAYASHI
AU - Atsushi TAKAHARA
AU - Kennosuke FUKAMI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.
ER -
English
