This paper presents an architecture for a table-lookup (TLU) engine that allows the real-time operation of complicated TLU for telecommunications, such as the longest prefix match (LPM) and the long-bit match in packet classification. The engine consists of many CAM (Content Addressable Memory) chips, which are classified into several groups. When actual TLU is performed, the entries in each CAM group are searched simultaneously, and the best entry candidate in each group is selected by an intra-group arbiter. The final output, the entry desired, is decided by an inter group arbiter that selects one group. This hierarchical structure of arbitration is the key to the scalability of the engine. To accelerate the operation speed of the engine, we introduce a novel mechanism called "hit-flag look-ahead" that sends a hit-flag signal from each matched CAM chip to the inter group arbiter before each intra group arbiter calculates the best CAM output in the group. We show that a TLU engine based on the above architecture achieves significantly fast performance compared to engines based on conventional techniques, especially in the case of a large number of entries with long-bit matching. Furthermore, our architecture can realize an 33.3 Mlps (lookups per second) within a 128 bit 300,000-entry table at wire speed.

Many studies have revealed that the performance of software-based Virtual Network Functions (VNFs) is insufficient for mission-critical networks. Scaling-out approaches, such as auto-scaling of VNFs, could handle a huge amount of traffic; however, the exponential traffic growth confronts us the limitations of both expandability of physical resources and complexity of their management. In this paper, we propose a fast datapath processing method called Packet Aggregation Flow (PA-Flow) that is based on hop-by-hop packet aggregation for more efficient Service Function Chaining (SFC). PA-Flow extends a notion of existing intra-node packet aggregation toward network-wide packet aggregation, and we introduce following three novel features. First, packet I/O overheads at intermediate network devices including NFV-nodes are mitigated by reduction of packet amount. Second, aggregated packets are further aggregated as going through the service chain in a hop-by-hop manner. Finally, next-hop aware packet aggregation is realized using OpenFlow-based flow tables. PA-Flow is designed to be available with various VNF forms (e.g. VM/container/baremetal-based) and virtual I/O technologies (e.g. vhost-user/SR-IOV), and its implementation does not bring noticeable delay for aggregation. We conducted two evaluations: (i) a baseline evaluation for understanding fundamental performance characteristics of PA-Flow (ii) a simulation-based SFC evaluation for proving PA-Flow's effect in a realistic environment. The results showed that throughput of short packet forwarding was improved by 4 times. Moreover, the total number of packets was reduced by 93% in a large-scale SFC.

This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

The recent widespread use of high-performance terminals has resulted in a rapid increase in mobile data traffic. Therefore, public wireless local area networks (WLANs) are being used often to supplement the cellular networks. Capacity improvement through the dense deployment of access points (APs) is being considered. However, the effective throughput degrades significantly when many users connect to a single AP. In this paper, users are classified into guaranteed bit rate (GBR) users and best effort (BE) users, and we propose a network model to provide those services. In the proposed model, physical APs and the bandwidths are assigned to each service class dynamically using a virtual AP configuration and a virtualized backhaul network, for reducing the call-blocking probability of GBR users and improving the satisfaction degree of BE users. Finally, we evaluate the performance of the proposed model through simulation experiments and discuss its feasibility.

Software-Defined Networking (SDN) can be applied for managing application flows dynamically by a logically centralized SDN controller and SDN switches. Because one SDN switch can support just a few thousand forwarding rule installations per second, it is a barrier to dynamic and scalable application flow management. For this reason, it is essential to reduce the number of application flows if they are to be successfully managed. Nowadays, since much attention has been paid to developing a network service that reduces application delay, the allowable delay of application flows has become an important factor. However, there has been no work on minimizing the number of flows while satisfying end-to-end delay of flows. In this paper, we propose a method that can aggregate flows and minimize the number flows in a network while ensuring all flows satisfy their allowable delay in accordance with QoS or SLA. Since the problem is classified as NP-hard, we propose a heuristic algorithm. We compared the aggregation effect of the proposed method, simple aggregation method and optimal solution by simulation. In addition, we clarify the characteristics of the proposed method by performing simulations with various parameter settings. The results show that the proposed method decreases the number of rules than comparative aggregation method and has very shorter computational time than optimal solution.

The 5G mobile network environment has been studied and developed, and the concept of a vEPC (Virtualized Evolved Packet Core) has been introduced as a framework for Network Functions Virtualization (NFV). Machine-to-Machine (M2M) communications in 5G networks require much faster response than are possible in 4G networks. However, if both the control plane (C-plane) and the data plane (D-plane) functions of the EPC are migrated into a single vEPC server, M2M devices and other user equipments (UEs) share the same resources. To accommodate delay-sensitive M2M sessions in vEPC networks, not only signaling performance on the C-plane but also packet processing performance on the D-plane must be optimized. In this paper, we propose a method for optimizing resource assignment of C-plane and D-plane Virtualized Network Functions (VNFs) in a vEPC server, called the vEPC-ORA method. We distinguish the communications of M2M devices and smartphones and model the vEPC server by using queueing theory. Numerical analysis of optimal resource assignment shows that our proposed method minimizes the blocking rates of M2M sessions and smartphone sessions. We also confirmed that the mean packet processing time is kept within the allowable delay for each communication type, as long as the vEPC server has enough VM resources. Moreover, we study a resource granularity effect on the optimal resource assignment. Numerical analysis under a fixed number of hardware resources of MME and S/P-GW is done for various resource granularities of the vEPC server. The evaluation results of numerical analyses showed that the vEPC-ORA method derives the optimal resource assignment in practical calculation times.

Many public cloud datacenters have adopted the Edge-Overlay model which supports virtual switch-based network virtualization using IP tunneling. However, software-implemented virtual switches can cause performance degradation because the packet processing load can concentrate on a particular CPU core. As a result, such load concentration decreases and destabilizes the performance of virtual networks. Although multi-queue functions like Receive Side Scaling (RSS) can distribute the load onto multiple CPU cores, they still have performance problems such as IRQ core collision between priority flows as well as competitive resource use between host and guest machines for received packet processing. In this paper, we propose Virtual Switch Extension (VSE) that adaptively determines CPU core assignment for SoftIRQ to prevent performance degradation. VSE supports two types of SoftIRQ core selection mechanisms, on-the-fly or predetermined. In the on-the-fly mode, VSE selects a SoftIRQ core based on current CPU load to exploit low-loaded CPU resources. In the predetermined mode, SoftIRQ cores are assigned in advance to differentiate the performance of priority flows. This paper describes a basic architecture and implementation of VSE and how VSE assigns a SoftIRQ cores. Moreover, we evaluate fundamental throughput of various CPU assignment models in the predetermined mode. Finally, we evaluate the performance of a priority VM in two VM usecases, the client-usecase which is receive-oriented and the router-usecase which performs bi-directional communications. In the client-usecase, the throughput of the priority VM was improved by 31% compared with RSS when the priority VM had one dedicated core. In the router-usecase, the throughput was improved by 29% when three dedicated cores were provided for the VM.