Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches
Summary :
In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.6 pp.1072-1075
- Publication Date
- 1997/06/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section LETTER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
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Takao OZAWA, Takeshi YAMAGUCHI, "Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 6, pp. 1072-1075, June 1997, doi: .
Abstract: In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_6_1072/_p
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@ARTICLE{e80-a_6_1072,
author={Takao OZAWA, Takeshi YAMAGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches},
year={1997},
volume={E80-A},
number={6},
pages={1072-1075},
abstract={In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1072
EP - 1075
AU - Takao OZAWA
AU - Takeshi YAMAGUCHI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1997
AB - In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.
ER -
English
