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[Author] Takao OZAWA(3hit)

1-3hit
  • An Efficient Algorithm for Determining the Minimum Number of Parallel Processors Required to Process a Large Number of Parallel Tasks

    Takao OZAWA  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E72-E No:10
      Page(s):
    1141-1148

    In this paper considered is the problem of scheduling a large number of parallel tasks (tasks having the same release and due times) on parallel processors. It is assumed that tasks all require one unit processing time, and the release and due times are non-negative integers. Task sets each of which consists of parallel tasks are dealt with instead of individual tasks in the conventional manner. The minimum number of processors required to process the given task sets is obtained by increasing stepwise the number of processors. To this end the minimal subset of task sets which cannot be allocated to a certain fixed number of processors is determined by a linear-order breadth-first search using the result of task assignment in two different ways, one top-down and the other bottom-up. The time complexity of the overall procedure is O(min(n, m)(mn log n)) and the space complexity is O(nm), where n and m are the numbers of task sets and time slots respectively.

  • On the Acyclicity of Single-Source Single-Sink Planar Digraphs

    Takao OZAWA  Hiroshi OHTA  

     
    LETTER-Graph Theory

      Vol:
    E65-E No:12
      Page(s):
    756-757

    In this paper presented is a theorem: a planar digraph which is embedded in a plane and which has a single source and a single sink both lying on the outer face of the digraph, is acyclic, if and only if all the inner faces are acyclic. Hence the number of tiesets necessary and sufficient for guaranteeing the acyclicity of the digraph is equal to the nullity of the digraph.

  • Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches

    Takao OZAWA  Takeshi YAMAGUCHI  

     
    LETTER

      Vol:
    E80-A No:6
      Page(s):
    1072-1075

    In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.