A Balanced-Mesh Clock Routing Technique for Performance Improvement

Hidenori SATO; Hiroaki MATSUDA; Akira ONOZAWA

A Balanced-Mesh Clock Routing Technique for Performance Improvement

Hidenori SATO, Hiroaki MATSUDA, Akira ONOZAWA

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This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.8 pp.1489-1495

Publication Date: 1997/08/25

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Category: VLSI Design Technology and CAD

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Hidenori SATO, Hiroaki MATSUDA, Akira ONOZAWA, "A Balanced-Mesh Clock Routing Technique for Performance Improvement" in IEICE TRANSACTIONS on Fundamentals, vol. E80-A, no. 8, pp. 1489-1495, August 1997, doi: .
Abstract: This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_8_1489/_p

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@ARTICLE{e80-a_8_1489,
author={Hidenori SATO, Hiroaki MATSUDA, Akira ONOZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Balanced-Mesh Clock Routing Technique for Performance Improvement},
year={1997},
volume={E80-A},
number={8},
pages={1489-1495},
abstract={This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A Balanced-Mesh Clock Routing Technique for Performance Improvement
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1489
EP - 1495
AU - Hidenori SATO
AU - Hiroaki MATSUDA
AU - Akira ONOZAWA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1997
AB - This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.
ER -