Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
Summary :
A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2383-2389
- Publication Date
- 1999/11/25
- Publicized
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Tomoyuki YODA, Atsushi TAKAHASHI, "Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2383-2389, November 1999, doi: .
Abstract: A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2383/_p
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@ARTICLE{e82-a_11_2383,
author={Tomoyuki YODA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion},
year={1999},
volume={E82-A},
number={11},
pages={2383-2389},
abstract={A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2383
EP - 2389
AU - Tomoyuki YODA
AU - Atsushi TAKAHASHI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.
ER -
English
