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It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2431-2439

- Publication Date
- 1999/11/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category

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Kazunori INOUE, Wataru TAKAHASHI, Atsushi TAKAHASHI, Yoji KAJITANI, "Schedule-Clock-Tree Routing for Semi-Synchronous Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2431-2439, November 1999, doi: .

Abstract: It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2431/_p

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@ARTICLE{e82-a_11_2431,

author={Kazunori INOUE, Wataru TAKAHASHI, Atsushi TAKAHASHI, Yoji KAJITANI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Schedule-Clock-Tree Routing for Semi-Synchronous Circuits},

year={1999},

volume={E82-A},

number={11},

pages={2431-2439},

abstract={It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.},

keywords={},

doi={},

ISSN={},

month={November},}

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TY - JOUR

TI - Schedule-Clock-Tree Routing for Semi-Synchronous Circuits

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2431

EP - 2439

AU - Kazunori INOUE

AU - Wataru TAKAHASHI

AU - Atsushi TAKAHASHI

AU - Yoji KAJITANI

PY - 1999

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E82-A

IS - 11

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - November 1999

AB - It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

ER -