IEICE TRANSACTIONS on Fundamentals
A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Summary :
This paper presents a new approach to simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modelling dynamic reconfiguration than previously reported techniques. Our method, named Clock Morphing (CM), is based on modelling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration. We discuss problems associated with the other approaches to DRL simulation and describe the main principles behind the proposed technique. We further demonstrate feasibility of a CM DRL simulation on its example implementation in VHDL.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2465-2474
- Publication Date
- 1999/11/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Milan VASILKO, David CABANIS, "A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2465-2474, November 1999, doi: .
Abstract: This paper presents a new approach to simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modelling dynamic reconfiguration than previously reported techniques. Our method, named Clock Morphing (CM), is based on modelling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration. We discuss problems associated with the other approaches to DRL simulation and describe the main principles behind the proposed technique. We further demonstrate feasibility of a CM DRL simulation on its example implementation in VHDL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2465/_p
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@ARTICLE{e82-a_11_2465,
author={Milan VASILKO, David CABANIS, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy},
year={1999},
volume={E82-A},
number={11},
pages={2465-2474},
abstract={This paper presents a new approach to simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modelling dynamic reconfiguration than previously reported techniques. Our method, named Clock Morphing (CM), is based on modelling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration. We discuss problems associated with the other approaches to DRL simulation and describe the main principles behind the proposed technique. We further demonstrate feasibility of a CM DRL simulation on its example implementation in VHDL.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2465
EP - 2474
AU - Milan VASILKO
AU - David CABANIS
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - This paper presents a new approach to simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modelling dynamic reconfiguration than previously reported techniques. Our method, named Clock Morphing (CM), is based on modelling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration. We discuss problems associated with the other approaches to DRL simulation and describe the main principles behind the proposed technique. We further demonstrate feasibility of a CM DRL simulation on its example implementation in VHDL.
ER -
English
