IEICE TRANSACTIONS on Fundamentals
An Analog CMOS Approximate Identity Neural Network with Stochastic Learning and Multilevel Weight Storage
Summary :
In this paper CMOS VLSI circuit solutions are suggested for on-chip learning and weight storage, which are simple and silicon area efficient. In particular a stochastic learning scheme, named Random Weight Change, and a multistable weight storage approach have been implemented. Additionally, the problems of the influence of technological variations on learning accuracy is discussed. Even though both the learning scheme and the weight storage are quite general, in the paper we will refer to a class of networks, named Approximate Identity Neural Networks, which are particularly suitable to be implemented with analog CMOS circuits. As a test vehicle a small network with four neurons, 16 weights, on chip learning and weight storage has been fabricated in a 1.2 µm double-metal CMOS process.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.7 pp.1344-1357
- Publication Date
- 1999/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Neural Networks
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Massimo CONTI, Paolo CRIPPA, Giovanni GUAITINI, Simone ORCIONI, Claudio TURCHETTI, "An Analog CMOS Approximate Identity Neural Network with Stochastic Learning and Multilevel Weight Storage" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 7, pp. 1344-1357, July 1999, doi: .
Abstract: In this paper CMOS VLSI circuit solutions are suggested for on-chip learning and weight storage, which are simple and silicon area efficient. In particular a stochastic learning scheme, named Random Weight Change, and a multistable weight storage approach have been implemented. Additionally, the problems of the influence of technological variations on learning accuracy is discussed. Even though both the learning scheme and the weight storage are quite general, in the paper we will refer to a class of networks, named Approximate Identity Neural Networks, which are particularly suitable to be implemented with analog CMOS circuits. As a test vehicle a small network with four neurons, 16 weights, on chip learning and weight storage has been fabricated in a 1.2 µm double-metal CMOS process.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_7_1344/_p
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@ARTICLE{e82-a_7_1344,
author={Massimo CONTI, Paolo CRIPPA, Giovanni GUAITINI, Simone ORCIONI, Claudio TURCHETTI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analog CMOS Approximate Identity Neural Network with Stochastic Learning and Multilevel Weight Storage},
year={1999},
volume={E82-A},
number={7},
pages={1344-1357},
abstract={In this paper CMOS VLSI circuit solutions are suggested for on-chip learning and weight storage, which are simple and silicon area efficient. In particular a stochastic learning scheme, named Random Weight Change, and a multistable weight storage approach have been implemented. Additionally, the problems of the influence of technological variations on learning accuracy is discussed. Even though both the learning scheme and the weight storage are quite general, in the paper we will refer to a class of networks, named Approximate Identity Neural Networks, which are particularly suitable to be implemented with analog CMOS circuits. As a test vehicle a small network with four neurons, 16 weights, on chip learning and weight storage has been fabricated in a 1.2 µm double-metal CMOS process.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - An Analog CMOS Approximate Identity Neural Network with Stochastic Learning and Multilevel Weight Storage
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1344
EP - 1357
AU - Massimo CONTI
AU - Paolo CRIPPA
AU - Giovanni GUAITINI
AU - Simone ORCIONI
AU - Claudio TURCHETTI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 1999
AB - In this paper CMOS VLSI circuit solutions are suggested for on-chip learning and weight storage, which are simple and silicon area efficient. In particular a stochastic learning scheme, named Random Weight Change, and a multistable weight storage approach have been implemented. Additionally, the problems of the influence of technological variations on learning accuracy is discussed. Even though both the learning scheme and the weight storage are quite general, in the paper we will refer to a class of networks, named Approximate Identity Neural Networks, which are particularly suitable to be implemented with analog CMOS circuits. As a test vehicle a small network with four neurons, 16 weights, on chip learning and weight storage has been fabricated in a 1.2 µm double-metal CMOS process.
ER -
English
