IEICE TRANSACTIONS on Fundamentals
Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Summary :
We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2400-2408
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Architecture
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Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, "Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2400-2408, December 2000, doi: .
Abstract: We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2400/_p
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@ARTICLE{e83-a_12_2400,
author={Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition},
year={2000},
volume={E83-A},
number={12},
pages={2400-2408},
abstract={We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2400
EP - 2408
AU - Kazutoshi KOBAYASHI
AU - Masanao YAMAOKA
AU - Yukifumi KOBAYASHI
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
ER -
English
