IEICE TRANSACTIONS on Fundamentals
A New Algorithm for the Configuration of Fast Adder Trees
Summary :
This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2426-2430
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Architecture
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Alberto PALACIOS-PAWLOVSKY, "A New Algorithm for the Configuration of Fast Adder Trees" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2426-2430, December 2000, doi: .
Abstract: This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2426/_p
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@ARTICLE{e83-a_12_2426,
author={Alberto PALACIOS-PAWLOVSKY, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Algorithm for the Configuration of Fast Adder Trees},
year={2000},
volume={E83-A},
number={12},
pages={2426-2430},
abstract={This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A New Algorithm for the Configuration of Fast Adder Trees
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2426
EP - 2430
AU - Alberto PALACIOS-PAWLOVSKY
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.
ER -
English
