IEICE TRANSACTIONS on Fundamentals
Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit
Summary :
This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2488-2497
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Co-design and High-level Synthesis
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Tae-Suh PARK, Chong-Ho LEE, Duck-Jin CHUNG, "Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2488-2497, December 2000, doi: .
Abstract: This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2488/_p
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@ARTICLE{e83-a_12_2488,
author={Tae-Suh PARK, Chong-Ho LEE, Duck-Jin CHUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit},
year={2000},
volume={E83-A},
number={12},
pages={2488-2497},
abstract={This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2488
EP - 2497
AU - Tae-Suh PARK
AU - Chong-Ho LEE
AU - Duck-Jin CHUNG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.
ER -
English
