The Ubiquitous sensor network (USN) node is required to operate for several months with limited system resources such as memory and power. The typical USN node is in the active state for less than 1% of its several month lifetime and waits in the inactive state for the remaining 99% of its lifetime. This paper suggests a power adjustment dual priority scheduler (PA-DPS) that offers low power consumption while meeting the USN requirements by estimating power consumption in the USN node. PA-DPS has been designed based on the event-driven approach and the dual-priority scheduling structure, which has been conventionally suggested in the real-time system field. From experimental results, PA-DPS reduced the inactive mode current up to 40% under the 1% duty cycle.

This paper presents an evolutionary technique to build and maintain fault-recoverable digital circuits. As the synthesis of a circuit by genetic algorithm is progressed according to the circuit behavioral objectives and interactions with the environments, the knowledge regarding the architecture as well as the placement and routing processes is not the major concern of the proposed method. The evolutionary behavior of the circuit also prevents the circuit from stuck-at faults by continuously modifying the neighboring circuit blocks accordingly. This is done without the prior knowledge of where and how the faults occur because of the evolutionary nature. Thus, the overhead circuit blocks for fault diagnosis and redundancy are minimized with this design. The fault-recoverable evolvable hardware circuits are synthesized to build a few combinational logics by evolution and the fault recovery capabilities are shown with the reconfigurable FPGA.

A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

This paper presents a novel low-cost high-performance CAVLC decoder for H.264/AVC. The proposed CAVLC decoder generates the length of coeff_token and total_zeros symbols with simple arithmetic operation. So, it can be implemented with reduced look-up table. And we propose multi-symbol run_before decoder which has enhanced throughput. It can decode more than 2.5 symbols in a cycle if there are run_before symbols to be decoded. The hardware cost is about 12 K gates when synthesized at 125 MHz.