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Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm

Barry SHACKLEFORD, Etsuko OKUSHI, Mitsuhiro YASUDA, Hisao KOIZUMI, Katsuhiko SEO, Hiroto YASUURA

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Summary :

The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2528-2537
Publication Date
2000/12/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Logic Synthesis

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