IEICE TRANSACTIONS on Fundamentals
Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Summary :
The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2528-2537
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
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Keyword
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Barry SHACKLEFORD, Etsuko OKUSHI, Mitsuhiro YASUDA, Hisao KOIZUMI, Katsuhiko SEO, Hiroto YASUURA, "Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2528-2537, December 2000, doi: .
Abstract: The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2528/_p
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@ARTICLE{e83-a_12_2528,
author={Barry SHACKLEFORD, Etsuko OKUSHI, Mitsuhiro YASUDA, Hisao KOIZUMI, Katsuhiko SEO, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm},
year={2000},
volume={E83-A},
number={12},
pages={2528-2537},
abstract={The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2528
EP - 2537
AU - Barry SHACKLEFORD
AU - Etsuko OKUSHI
AU - Mitsuhiro YASUDA
AU - Hisao KOIZUMI
AU - Katsuhiko SEO
AU - Hiroto YASUURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (BCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.
ER -
English
