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A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.6 pp.1192-1198

- Publication Date
- 2000/06/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- Analog Signal Processing

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Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, "A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1192-1198, June 2000, doi: .

Abstract: A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1192/_p

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@ARTICLE{e83-a_6_1192,

author={Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC},

year={2000},

volume={E83-A},

number={6},

pages={1192-1198},

abstract={A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.},

keywords={},

doi={},

ISSN={},

month={June},}

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TY - JOUR

TI - A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1192

EP - 1198

AU - Byung-Woog CHO

AU - Pyung CHOI

AU - Jun-Rim CHOI

AU - Dae-Hyuk KWON

AU - Byung-Ki SOHN

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 6

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - June 2000

AB - A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.

ER -