IEICE TRANSACTIONS on Fundamentals
A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
Summary :
In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.8 pp.1663-1672
- Publication Date
- 2000/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Akihisa OHTA, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, "A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 8, pp. 1663-1672, August 2000, doi: .
Abstract: In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_8_1663/_p
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@ARTICLE{e83-a_8_1663,
author={Akihisa OHTA, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath},
year={2000},
volume={E83-A},
number={8},
pages={1663-1672},
abstract={In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1663
EP - 1672
AU - Akihisa OHTA
AU - Tsuyoshi ISSHIKI
AU - Hiroaki KUNIEDA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2000
AB - In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.
ER -
English
