In the 5G era, centralized mobility management raises the issue of traffic concentration on the mobility anchor. Distributed mobility management is expected to be a solution for this issue, as it moves mobility anchor functions to multiple edge routers. However, it incurs path stretch and redundant traffic on the backhaul links. Although these issues were not considered important in the 3G/4G era, they are expected to be a serious problem in the 5G era. In this paper, we design a routing-based mobility management mechanism to address the above problems. The mechanism integrates distributed routing with Bloom Filters and an anchor-less scheme where edge routers work as mobility anchors. Simulations show that the proposed mechanism achieves a good balance between redundant traffic on the backhaul links and routing overhead.

Internet of Things (IoT) devices, which have different characteristics in mobility and communication patterns from traditional mobile devices such as cellular phones, have come into existence as a new type of mobile devices. A strict mobility management scheme for providing highly mobile devices with seamless access is over-engineered for IoT devices' mobility management. We revisit current mobility management schemes for wireless mobile networks based on identifier/locator separation. In this paper, we focus on IoT communication patterns, and propose a new routing-based mobility scheme for them. Our scheme adopts routing information aggregation scheme using the Bloom Filter as a data structure to store routing information. We clarify the effectiveness of our scheme in IoT environments with a large number of IoT devices, and discuss its deployment issues.

Failure avoidance capability is a desired feature for telecommunication networks, such as the Internet. However, not all failures can be promptly bypassed on the Internet because routing systems that are responsible for detecting and avoiding failures cannot detect all failures. Consequently, failures can interrupt internet communications for a long time, such as a few hours. This paper proposes a novel routing architecture called Drouting that enables flexible failure avoidance. In Drouting, routers calculate multipaths from a source to a destination by constructing Directed Acyclic Graphs (DAGs) that include all links in the intra-domain network graph. IP packets carry packet tags that are set by the end host. The packet tags are used to select a network path from the multipath routes. In this paper, the failure avoidance property of Drouting architecture is evaluated through comparison with another proposal, Deflection, using simulations. Simulations were performed on inferred and synthetic topologies. Drouting exhibits similar performance with Deflection in terms of the number of nexthops, the number of paths and the length of paths, while Drouting outperforms Deflection in the probability of success of failure avoidance.

The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.

In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.

The mapping from a global routing to a feasible detailed routing in a number of 2D array routing structures has been shown to be an NP-complete problem. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA routing structures called Greedy Routing Architectures (GRAs) have been proposed. On GRAs, optimally routing each switch box, in a specified order, leads to an optimal chip routing. Because routing each switch box takes polynomial time, the mapping problem on GRAs can be solved in polynomial time. In particular, an H-tree GRA with W2+2W switches per switch box (SpSB) and a 2D array GRA with 4W2+2W SpSB have been proposed. In this paper, we improve on these results by introducing an H-tree GRA with W2/2+2W SpSB and a 2D array GRA with 3.5W2+2W SpSB. These new GRAs have the same desirable mapping properties of the previously described GRAs, but use fewer switches.