IEICE TRANSACTIONS on Fundamentals
A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
Summary :
This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2690-2696
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- FPGA Systhesis
Authors
Keyword
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Chi-Chou KAO, Yen-Tai LAI, "A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2690-2696, November 2001, doi: .
Abstract: This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2690/_p
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@ARTICLE{e84-a_11_2690,
author={Chi-Chou KAO, Yen-Tai LAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs},
year={2001},
volume={E84-A},
number={11},
pages={2690-2696},
abstract={This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2690
EP - 2696
AU - Chi-Chou KAO
AU - Yen-Tai LAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
ER -
English
