IEICE TRANSACTIONS on Fundamentals
A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate
Summary :
In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.6 pp.1479-1487
- Publication Date
- 2001/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Thanyapat SAKUNKONCHAK, Sawasd TANTARATANA, "A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1479-1487, June 2001, doi: .
Abstract: In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1479/_p
Copy
@ARTICLE{e84-a_6_1479,
author={Thanyapat SAKUNKONCHAK, Sawasd TANTARATANA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate},
year={2001},
volume={E84-A},
number={6},
pages={1479-1487},
abstract={In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1479
EP - 1487
AU - Thanyapat SAKUNKONCHAK
AU - Sawasd TANTARATANA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.
ER -
English
