IEICE TRANSACTIONS on Fundamentals
A Semi-Synchronous Circuit Design Method by Clock Tree Modification
Summary :
A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2596-2602
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Design
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Seiichiro ISHIJIMA, Tetsuaki UTSUMI, Tomohiro OTO, Atsushi TAKAHASHI, "A Semi-Synchronous Circuit Design Method by Clock Tree Modification" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2596-2602, December 2002, doi: .
Abstract: A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2596/_p
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@ARTICLE{e85-a_12_2596,
author={Seiichiro ISHIJIMA, Tetsuaki UTSUMI, Tomohiro OTO, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Semi-Synchronous Circuit Design Method by Clock Tree Modification},
year={2002},
volume={E85-A},
number={12},
pages={2596-2602},
abstract={A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Semi-Synchronous Circuit Design Method by Clock Tree Modification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2596
EP - 2602
AU - Seiichiro ISHIJIMA
AU - Tetsuaki UTSUMI
AU - Tomohiro OTO
AU - Atsushi TAKAHASHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.
ER -
English
