IEICE TRANSACTIONS on Fundamentals
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Summary :
In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2746-2755
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Clock Scheduling
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Keiichi KUROKAWA, Takuya YASUI, Yoichi MATSUMURA, Masahiko TOYONAGA, Atsushi TAKAHASHI, "A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2746-2755, December 2002, doi: .
Abstract: In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2746/_p
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@ARTICLE{e85-a_12_2746,
author={Keiichi KUROKAWA, Takuya YASUI, Yoichi MATSUMURA, Masahiko TOYONAGA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling},
year={2002},
volume={E85-A},
number={12},
pages={2746-2755},
abstract={In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2746
EP - 2755
AU - Keiichi KUROKAWA
AU - Takuya YASUI
AU - Yoichi MATSUMURA
AU - Masahiko TOYONAGA
AU - Atsushi TAKAHASHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.
ER -
English
