The search functionality is under construction.
The search functionality is under construction.

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling

Keiichi KUROKAWA, Takuya YASUI, Yoichi MATSUMURA, Masahiko TOYONAGA, Atsushi TAKAHASHI

  • Full Text Views

    0

  • Cite this

Summary :

In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2746-2755
Publication Date
2002/12/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Clock Scheduling

Authors

Keyword