IEICE TRANSACTIONS on Fundamentals
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Summary :
In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2775-2784
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Design
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Shinya YAMASAKI, Shingo NAKAYA, Shin'ichi WAKABAYASHI, Tetsushi KOIDE, "A Performance-Driven Floorplanning Method with Interconnect Performance Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2775-2784, December 2002, doi: .
Abstract: In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2775/_p
Copy
@ARTICLE{e85-a_12_2775,
author={Shinya YAMASAKI, Shingo NAKAYA, Shin'ichi WAKABAYASHI, Tetsushi KOIDE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Performance-Driven Floorplanning Method with Interconnect Performance Estimation},
year={2002},
volume={E85-A},
number={12},
pages={2775-2784},
abstract={In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2775
EP - 2784
AU - Shinya YAMASAKI
AU - Shingo NAKAYA
AU - Shin'ichi WAKABAYASHI
AU - Tetsushi KOIDE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.
ER -
English
