We propose an optimization method for power distribution network that explicitly deals with timing. We have found and focused on the facts that decoupling capacitance (decap) does not necessarily improve gate delay depending on the switching timing within a cycle and that power wire expansion may locally degrade the voltage. To resolve the above facts, we devised an efficient sensitivity calculation of timing to decap size and power wire width for guiding optimization. The proposed method, which is based on statistical noise modeling and timing analysis, accelerates sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that decap allocation based on the sensitivity analysis efficiently minimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 3.13% even while the total amount of decaps is reduced to 40%. The wire sizing with the proposed method also efficiently reduces required wire resource necessary to attain the same circuit delay by 11.5%.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.