IEICE TRANSACTIONS on Fundamentals
Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications
Summary :
This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hardware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2813-2821
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Spread Spectrum Techniques and Applications)
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Hsi-Pin MA, Steve Hengchen HSU, Tzi-Dar CHIUEH, "Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2813-2821, December 2002, doi: .
Abstract: This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hardware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2813/_p
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@ARTICLE{e85-a_12_2813,
author={Hsi-Pin MA, Steve Hengchen HSU, Tzi-Dar CHIUEH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications},
year={2002},
volume={E85-A},
number={12},
pages={2813-2821},
abstract={This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hardware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2813
EP - 2821
AU - Hsi-Pin MA
AU - Steve Hengchen HSU
AU - Tzi-Dar CHIUEH
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hardware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.
ER -
English
