This paper describes the design and measurements of two-gain-mode MMIC power amplifier modules (PAMs) for Band 1 and Band 5 WCDMA data communications. The PAMs are based on the two-stage single-chain amplifier topology with an L-shaped FET step attenuator (ATT) placed at the interstage, featuring not only high-efficiency operation but also both a small phase discontinuity and a small input return loss variation between the two gain modes: a high-gain mode (0-dB thru state for the ATT) and a low-gain mode (14-dB attenuation state for the ATT). The PAMs are assembled on a 3 mm × 3 mm FR-4 laminate together with several surface mount devices, and a high-directivity, 20-dB bilayer-type directional coupler is integrated on the laminate for accurate forward-power monitoring even under a 2.5:1-VSWR load mismatching condition. To validate the design and analysis for the PAMs using the L-shaped ATT, two PAM products — a Band 1 PAM and a Band 5 PAM — were fabricated using our in-house GaAs-BiFET process. The main RF measurements under the condition of a WCDMA (R99) modulated signal and a 3.4-V supply voltage are as follows. The Band 1 PAM can deliver a power-added efficiency (PAE) as high as 46% at an output power (Pout) of 28.25 dBm while maintaining a ±5-MHz-offset adjacent channel power ratio (ACLR1) of approximately -40 dBc or less and a small phase discontinuity of less than 5°. The Band 5 PAM can also deliver a high PAE of 46% at the same Pout and ACLR1 levels with small phase discontinuity of less than 4°. This small discontinuity is due to the phase-shift compensation capacitance embedded in the ATT. The measured input return loss is well maintained at better than 10 dB at the two modes. In addition, careful coupler design achieves a small detection error of less than 0.5 dB even under a 2.5:1-VSWR load mismatching condition.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.

A wide-tuning-range LC-tuned voltage-controlled oscillator (LC-VCO) – featuring small VCO-gain (KVCO) variation – has been developed. For small KVCO variation, a serial LC-resonator that consists of an inductor, a fine-tuning varactor, and a capacitor bank was added to a conventional parallel LC-resonator that uses a capacitor bank scheme. The resonator was applied to a 3.9-GHz VCO for multi-band W-CDMA RFIC fabricated using 0.25-µm Si-BiCMOS technology. The VCO exhibited KVCO variation of only 21%, which is one third that of a conventional VCO, with a 34% tuning range. The VCO also exhibited a low phase noise of -121 dBc/Hz at 1-MHz offset frequency and a low current consumption of 6.0 mA.

This paper presents a new generalized single threshold model that can be used in communications and cellular networks. In the proposed model, called Single Hysteresis Model (SHM), it is assumed that the amount of resources accessible for a new call of a given class can depend on two load areas of the system. The switching between areas is modulated by the two-state Markov chain which determines the average time the system spends in a particular load area, i.e. the area in which calls of selected classes with a reduced amount of resources (high load area) and with the initial amount of resources (low load area) are serviced. The results obtained for the discussed analytical model are compared with the results of the simulation of an exemplary WCDMA radio interface carrying a mixture of different multi-rate traffic streams. The research study confirms high accuracy of the proposed model.

We propose a new majority voting scheme for identifying downlink primary scrambling code, where two voting processes with different coherent correlation intervals (CCIs) are simultaneously performed. A false alarm probability and a threshold adjustment for the proposed scheme are investigated, and it is shown by computer simulations that the proposed scheme can perform well over a wide range of frequency offsets.

This paper investigates the performance of ARQ-aided downlink Time Switched Transmit Diversity (TSTD) in the WCDMA Low Chip Rate (LCR)-Time Division Duplex (TDD) system, when antenna switching and power ramping are applied. With the help of the ARQ signal, where the receiver sends the acknowledgement (ACK or NACK) to the transmitter, the proposed TSTD scheme switches the transmit antenna and ramps up the transmission power for the retransmitted data, when the transmitter receives a NACK signal. Simulation results demonstrate, that when the mobile speed is 3 km/h and a frame error rate (FER) is set to 1%, the antenna switching scheme yields 2 dB to 3 dB performance gain in terms of average Eb/N0, and the power ramping gives 0.7 dB to 1.6 dB gain, compared with the conventional ARQ-aided TSTD. In addition, 6% of throughput gain is shown by amalgamating the antennas switching as well as the power ramping, when the average Eb/N0 is equal to 0 dB.

In this paper, we analyze the coexistence issues of M-WiMAX TDD and WCDMA FDD systems. Smart antenna techniques are applied to mitigate the performance loss induced by adjacent channel interference (ACI) in the scenarios where performance is heavily degraded. In addition, an ACI model is proposed to capture the effect of transmit beamforming at the M-WiMAX base station. Furthermore, a MCS-based throughput analysis is proposed, to jointly consider the effects of ACI, system packet error rate requirement, and the available modulation and coding schemes, which is not possible by using the conventional Shannon equation based analysis. From the results, we find that the proposed MCS-based analysis method is quite suitable to analyze the system theoretical throughput in a practical manner.

In this paper, an indoor repeater antenna with high isolation for WCDMA application is proposed. The designed repeater has very small separation of 20 mm between the donor and server antennas. The antenna has two resonance frequencies to cover the WCDMA band from 1.92 GHz to 2.17 GHz. The fabricated antenna has VSWR below 1.5, gain over 8 dBi, and isolation between server and donor antennas less than -80 dB in the WCDMA band.

This paper presents the performance of DSTBC when applied on the downlink transmission of WCDMA cellular systems in fast-varying time-dispersive channels. First, three DSTBC-WCDMA receiver architectures are proposed and they are: (1) the DSTBC Rake receiver for combined-code (D-Rake-C), (2) the DSTBC deterministic receiver for combined-code (D-Det-C), and (3) the DSTBC deterministic de-prefix receiver for combined-code (D-Det-DP-C). Detection can be divided into a correlator that combines descrambling and despreading, and a DSTBC decoder. The correlator is designed to perform signal separation of the multipath-multiuser signal via least-square (LS) estimation. To enable the correlator to perform signal separation at every block period, the long combined spreading and scrambling codes are divided into shorter codes. Then, the proposed receivers are theoretically analyzed in time-dispersive channels and multiple-user environment using the moment generating function (MGF) of fading distributions. For analyzing interference tolerance, the standard Gaussian approximation is employed. Finally, simulations are performed. Theoretical performance well matches simulated results. Among the three receivers, the D-Det-DP-C receiver has the best performance in time-dispersive channels with a maximum excess delay of 4 chips and a maximum Doppler frequency of 250 Hz. Results also show minimal performance degradation for fast fading channels with a maximum Doppler frequency of 1200 Hz. The best performance is obtained when the receiver has the information on the maximum excess delay and all users' spreading codes.

A new random access channel (RACH) preamble detection scheme using variable coherent correlation intervals (CCIs) is proposed. It is shown first that it is enough to employ two CCIs for supporting a user equipment (UE) velocity of 300 km/h, and then a CCI selection criterion is proposed. Computer simulation results indicate that the proposed scheme can provide a robust detection performance in time-varying fading channel environments.

Mutual interference among users can abruptly increase othercell interference and cause overload situation in coexisting WCDMA and HSDPA systems. Traffic overloading can degrade the performance of the systems. This letter proposes a new dynamic downlink load control (DDLC) algorithm to reduce performance degradation due to overload in the coexistence of WCDMA and HSDPA systems. With the proposed algorithm, the downlink load is controlled according to load states classified by two load-control thresholds, and traffic overloading is alleviated by dynamically adjusting the CQI values reported by users, based on the downlink load as well as channel variations. The proposed algorithm is simulated and results show that the DDLC scheme improves the performance of both WCDMA and HSDPA systems in terms of outage probability, total system throughput, and radio resource utilization.

In this paper, we propose a Frequency Domain Equalizer (FDE) without inserting the Guard Interval (GI) at the transmitter which is applicable to the Wide-band Code Division Multiple Access (WCDMA) and Orthogonal Frequency-Division Multiplexing (OFDM) systems. The proposed FDE adopts the Overlap-Cut (OC) method to avoid the Inter-Block Interference (IBI) and exploits the decision feedback structure to improve the Bit Error Rate (BER) performance. Without inserting the GI, the proposed FDE will be compatible to the frame format of the current High Speed Downlink Packet Access (HSDPA). Besides, it can improve the BER performance and bandwidth utilization when the GI is less than the channel length of the OFDM system.

This article proposes a method that can calculate the blocking probability of multi-service cellular systems with Wideband Code Division Multiple Access radio interface. The method considers a finite and an infinite source population and takes into account the interdependency of calls service processes in neighboring cells and in both the uplink and the downlink directions. The basis of the proposed method is the fixed-point methodology. A comparison of the results of analytical calculations to those of simulations confirms the accuracy of the proposed method. The proposed scheme can realize cost-effective radio resource management in 3G mobile networks and can be easily applied to network capacity calculations.

Recently, multimedia services are increasing with the widespread use of various wireless applications such as web browsers, real-time video, and interactive games, which results in traffic asymmetry between the uplink and downlink. Hence, time division duplex (TDD) systems which provide advantages in efficient bandwidth utilization under asymmetric traffic environments have become one of the most important issues in future mobile cellular systems. It is known that two types of intercell interference, referred to as crossed-slot interference, additionally arise in TDD systems; the performances of the uplink and downlink transmissions are degraded by BS-to-BS crossed-slot interference and MS-to-MS crossed-slot interference, respectively. The resulting performance unbalance between the uplink and downlink makes network deployment severely inefficient. Previous works have proposed intelligent time slot allocation algorithms to mitigate the crossed-slot interference problem. However, they require centralized control, which causes large signaling overhead in the network. In this paper, we propose to change the shape of the cellular structure itself. The conventional cellular structure is easily transformed into the proposed cellular structure with distributed receive antennas (DRAs). We set up statistical Markov chain traffic model and analyze the bit error performances of the conventional cellular structure and proposed cellular structure under asymmetric traffic environments. Numerical results show that the uplink and downlink performances of the proposed cellular structure become balanced with the proper number of DRAs and thus the proposed cellular structure is notably cost-effective in network deployment compared to the conventional cellular structure. As a result, extending the conventional cellular structure into the proposed cellular structure with DRAs is a remarkably cost-effective solution to support asymmetric traffic environments in future mobile cellular systems.

This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

In this letter, the influence of the downlink average ratio of the other cell interference to other-user interference in the serving cell (DARI) on the distributed repeater system (DRS) performance is analyzed. It is found that the improvement of DARI depends on a propagation path loss environment. Applying the computed DARI to a 3-RS DRS cell, as high as 13.9% capacity enhancement was obtained when the path loss exponent is 4.5. In addition, by using the power allocation equation, it is expected that a hexagonal DRS cell without coverage holes or excessive coverage overlap can be realized.

Since a receiver (RX) and a transmitter (TX) are operated simultaneously in a WCDMA transceiver, noise and intermodulation distortion performances of a low-noise amplifier (LNA) are degraded by a large leakage signal from the TX. The degradation of the distortion due to the large leakage signal from the TX has been reported in some previous works, but to our best knowledge, there are no reports about the degradation of noise figure (NF) in a LNA due to the large leakage signal from the TX. In this paper, a 900-MHz LNA for WCDMA terminal with high tolerance for a leakage signal from the TX is proposed. Suitable designs of an input matching circuit and a trap circuit are adopted to improve the tolerance for the leakage signal from the TX. The LNA using the proposed techniques is fabricated using SiGe-BiCMOS process. The measured degradation of NF due to the leakage signal from the TX is suppressed to only 0.12 dB.

A fast fc automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled Gm-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of fc tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast fc automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average fc of 2.12 MHz.

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using a common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for integrating on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to DC current increase and intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using SiGe BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -10 dBm.