A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation

Hiroyuki TSUJIKAWA; Shozo HIRANO; Kenji SHIMAZAKI

A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation

Hiroyuki TSUJIKAWA, Shozo HIRANO, Kenji SHIMAZAKI

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Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.2974-2982

Publication Date: 2003/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Parasitics and Noise

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Hiroyuki TSUJIKAWA, Shozo HIRANO, Kenji SHIMAZAKI, "A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 2974-2982, December 2003, doi: .
Abstract: Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_2974/_p

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@ARTICLE{e86-a_12_2974,
author={Hiroyuki TSUJIKAWA, Shozo HIRANO, Kenji SHIMAZAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation},
year={2003},
volume={E86-A},
number={12},
pages={2974-2982},
abstract={Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2974
EP - 2982
AU - Hiroyuki TSUJIKAWA
AU - Shozo HIRANO
AU - Kenji SHIMAZAKI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.
ER -