Seed Selection Procedure for LFSR-Based Random Pattern Generators

Kenichi ICHINO; Ko-ichi WATANABE; Masayuki ARAI; Satoshi FUKUMOTO; Kazuhiko IWASAKI

Seed Selection Procedure for LFSR-Based Random Pattern Generators

Kenichi ICHINO, Ko-ichi WATANABE, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI

Full Text Views

0

Cite this

Summary :

We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2^m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by simple seeds, i.e. 0001, for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3063-3071

Publication Date: 2003/12/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Timing Verification and Test Generation

Cite this

Copy

Kenichi ICHINO, Ko-ichi WATANABE, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI, "Seed Selection Procedure for LFSR-Based Random Pattern Generators" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3063-3071, December 2003, doi: .
Abstract: We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2^m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by simple seeds, i.e. 0001, for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3063/_p

Copy

@ARTICLE{e86-a_12_3063,
author={Kenichi ICHINO, Ko-ichi WATANABE, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Seed Selection Procedure for LFSR-Based Random Pattern Generators},
year={2003},
volume={E86-A},
number={12},
pages={3063-3071},
abstract={We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2^m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by simple seeds, i.e. 0001, for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.},
keywords={},
doi={},
ISSN={},
month={December},}

Copy

TY - JOUR
TI - Seed Selection Procedure for LFSR-Based Random Pattern Generators
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3063
EP - 3071
AU - Kenichi ICHINO
AU - Ko-ichi WATANABE
AU - Masayuki ARAI
AU - Satoshi FUKUMOTO
AU - Kazuhiko IWASAKI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2^m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by simple seeds, i.e. 0001, for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.
ER -