IEICE TRANSACTIONS on Fundamentals
Implementation of Java Accelerator for High-Performance Embedded Systems
Summary :
A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3079-3088
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Simulation Accelerator
Authors
Keyword
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Motoki KIMURA, Morgan Hirosuke MIKI, Takao ONOYE, Isao SHIRAKAWA, "Implementation of Java Accelerator for High-Performance Embedded Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3079-3088, December 2003, doi: .
Abstract: A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3079/_p
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@ARTICLE{e86-a_12_3079,
author={Motoki KIMURA, Morgan Hirosuke MIKI, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Implementation of Java Accelerator for High-Performance Embedded Systems},
year={2003},
volume={E86-A},
number={12},
pages={3079-3088},
abstract={A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Implementation of Java Accelerator for High-Performance Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3079
EP - 3088
AU - Motoki KIMURA
AU - Morgan Hirosuke MIKI
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.
ER -
English
