The search functionality is under construction.

IEICE TRANSACTIONS on Fundamentals

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, Shinji KIMURA, Katsumasa WATANABE

  • Full Text Views

    0

  • Cite this

Summary :

In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3184-3191
Publication Date
2003/12/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Logic and High Level Synthesis

Authors

Keyword